Just wanted to share this ...
There are 4 application types that I know - commercial, industrial, military and JAN (only tested in the US). At Final Test, the lot travellers for these are very similar and the only difference is the temp and # of tests. The JAN application is same as the military however, the lot traveller is very thick and on close inspection, it is basically military but the tests are repeated over and over. The one that distinguishes industrial, military and JAN vs commercial is the package. Hermetic package is used such as metal can and ceramic as these have much more stable performance over a wide temp range.
The very first process to make DACs is the wafer fabrication where the parts (wafers) are laser trimmed to distinguish the grades. Since IC layout is the same for all the application types of a specified P/N, the laser trimming ensures that the different grades meet specified performance levels.
At Final Test to get JAN, the wafers that pass top grade military application are used. On first pass testing on JAN lot traveller, yield is typically around 1% to 25%. And after all tests are completed (based on information that I know) yield is typically less than 50% of first pass yield. Yield is quite low for JAN but gradually increases in Military, Industrial and Commercial application. In Commercial application, yield is typically in the high 80s and 90s.
For a design to meet all four application types is very tough. The design process and development is long and hard. Only outstanding electrical designs make it. Things such as:
(1) The IC layout compliance with the wafer fabrication processes and requirements
(2) Short test times both at Wafer fabrication and Final Test
- There is a trial run on all designs. And, one need to justify test set-up costs. Test times must also comply with standards - with test time for one part taking from >30 seconds to a few minutes depending on DAC P/N and tester used, it takes much time to complete lot size of 500. Since tests is typically done at 3 temperatures it becomes frustrating if one encounters problem during testing. Add the QA test after Final Test and you know how precious time is for DACs.
(3) Overall yield and yield to grade should justify development costs to ensure ROI
This make the DAC designers job very difficult.
It is with this reason that I look at the architecture, specs and history of a particular DAC. There is a story behind each one and for me it is good to know what people went through to develop it.